A microprocessor may be designed to interrupt the execution of a program and switch to a subroutine upon receiving an interrupt signal. This makes it possible to nearly instantaneously process asynchronous events. Such a microprocessor is therefore capable of receiving various interrupt signals from peripherals internal or external to the microprocessor. The internal peripherals are generally communications peripherals that prompt an interrupt of a program for the priority processing of a specified task.
In practice, several interrupt signals may be applied simultaneously (i.e., in parallel) to a microprocessor. An interrupt controller manages priorities of the interrupt requests. The interrupt controller first processes the interrupt with the highest priority according to a hierarchy of predetermined priorities. The interrupt controller also manages an interrupt vector for switching the microprocessor to an interrupt subroutine corresponding to the interrupt signal to be processed.
The implementation of an interrupt mechanism within a microprocessor requires some precautions. This is because a certain period of time elapses between the instant at which the core of a microprocessor detects an interrupt request and the instant at which it processes this request. The withdrawal of an interrupt request between these two instants may cause the microprocessor to malfunction for reasons that will be understood more clearly with reference to FIG. 1.
A diagrammatic view of an exemplary architecture of a microprocessor MP including an interrupt circuit or means is shown in FIG. 1. The microprocessor is of the microcontroller type and includes a central processing unit CPU, an interrupt controller ITC, and a memory array that are integrated on the same silicon chip. In this example, the unit CPU is connected to the memory array by a 16-bit address bus ADB and an 8-bit data bus DTB. The memory array includes a program memory PMEM which may include, for example, an electrically erasable and programmable FLASH memory and a random-access data memory (RAM) DMEM.
The CPU includes a core CORE and registers, among which there is a program counter register PCR, an accumulator register ACCU, a condition code register CCR (including flags of the microprocessor), and a stack pointer register SP. Since the illustrated microprocessor operates based upon 8 data bits and 16 address bits, the register PCR includes a most significant bit register PCRH and a least significant bit register PCRL. The registers PCRH, PCRL respectively include the 8 most significant address bits and the 8 least significant address bits of the address of the instruction being executed. Similarly, the register SPR includes a register SPRH and a register SPRL respectively including the 8 most significant bits and the 8 least significant bits of the address of the top of the stack STK.
The stack STK is a reserved zone of the random-access memory DMEM used to save a “context” during the jump to a subroutine or during the execution of PUSH or POP type instructions (corresponding to the stacking or unstacking of data in the stack). The context represents a set of data present in the registers of the CPU whose values depend on the program being executed. In this case, the context is the contents of the registers PCRH, PCRL, ACCU, CCR.
The interrupt controller ITC is a wired logic decoder equipped with N inputs to receive N interrupt signals IT1 to ITN. When a peripheral element applies an interrupt signal ITx to the microprocessor, the signal ITx is received by one of the inputs IT1 to ITN of the controller ITC. The controller ITC then delivers an interrupt request IRQ and an interrupt vector ITVECx to the core of the CPU. When the CPU detects the request IRQ, it terminates execution of the instruction in progress, increments the program counter PC, and then processes the interrupt. This processing conventionally includes saving the context in the stack STK, sending an interrupt acknowledge signal ITACK and determining the address the interrupt subroutine using the interrupt vector ITVECx, and reading and executing the first instruction of the subroutine and then of the following instructions. After execution of the interrupt subroutine, the microprocessor restores the context saved in the stack and resumes execution of the program (unless a new interrupt request IRQ sends switches the microprocessor to a new interrupt subroutine).
As noted above, there is a risk that the peripheral that sent the interrupt signal ITx will withdraw this signal before the core of the CPU has time to determine the address of the interrupt subroutine using the interrupt vector ITVECx. To resolve this problem, two precautions are generally taken. First, it is recommended in the data sheets of microprocessors that an interrupt should be held until the acknowledgment ITACK is sent. Second, should the suggestion in the data sheet not be complied with by a peripheral, the controller ITC is designed to deliver a default interrupt vector ITVECRST that routes the CPU to an address in which there is a resetting instruction RST. Accordingly, if a peripheral withdraws the interrupt signal ITx before the CPU has time to read the interrupt vector ITVECx, the default interrupt vector delivered by the controller ITC is the vector ITVECRST which prompts the software resetting (pseudo-RESET) of the microprocessor.
In practice, it is also the case that electrical or electromagnetic disturbances prompt the appearance of parasitic and ephemeral interrupt signals at the inputs of the decoder ITC which give rise to untimely resettings of the microprocessor. Indeed, the CPU may detect an interrupt request IRQ but, after saving the context, it may receive the interrupt vector ITVECRST.